1. Field of the Invention
The invention as disclosed relates to a device and manufacturing method for semiconductor devices and specifically devices having an insulated gate electrode.
2. Description of the Prior Art
As microfabrication causes insulated-gate field effect transistors to decrease in size, a potential difference near the drain rapidly increases. This could result in electrons or holes ("hot carriers") that have been accelerated by such potential difference to exhibit bad behavior. This in turn leads to several problems. This problem becomes more serious especially for the so-called "submicron" devices with channel lengths less than or equal to one micrometer (.mu.m).
In those transistors (thin-film transistors, for example) employing certain semiconductor materials with grain boundaries such as polycrystalline semiconductor, the potential-difference increase might also increase leakage current upon application of a reverse bias voltage to the gate electrode (in the turned-off state). To avoid this, it should be required that the near-the-drain potential difference be decreased or "moderated". Several types of insulated-gate field effect transistors of different structures have been proposed for this purpose.
One typical transistor structure shown in FIG. 3A is generally known as the offset gate type which is structured in a manner such that it has a source 32 and drain 33 with an intrinsic (or of the opposite conductivity type to that of the source/drain) semiconductor layer (active layer) 31 being laid between them. This system also has a gate electrode 35 overlying an active layer 31 with a gate insulation film 34 being sandwiched therebetween them. The gate electrode 35 is laterally spaced apart from the drain 33 by a predefined distance x.sub.1. An electric field as created near the drain is weakened or moderated enabling elimination of hot carriers' contribution.
Another prior known transistor structure is shown in FIG. 3B. This is called the lightly-doped drain (LDD) structure and is disclosed in Examined Published Japanese Patent Application No. 3-38755. An impurity concentration-reduced region (lightly doped impurity region) 37 is provided between the drain 33 and active layer 31. This region is the same in conductivity type as drain 33. A similar lightly doped impurity region 36 may also be provided between the source 32 and active layer 31. With such an arrangement, the lightly doped region 37 acts as a buffer region which may weaken the electric field near the drain.
The offset gate structure may be successfully fabricated by anode-oxidization or "anodization" of the gate electrode as described in Unexamined Published Japanese Patent Application Nos. 6-338612, 7-226515. As shown in FIG. 3C, the gate electrode is located spaced from the source/drain by a selected distance corresponding to the thickness x.sub.2 of an anodized oxide 38. This effectively performs a self-alignment doping process using the anodized oxide 38, by letting the gate electrode be anodized at its side wall for formation of the source 32 and drain 33.
Similarly, the lightly doped impurity region may also be fabricated successfully by anodizing the gate electrode as taught from Unexamined Published Japanese Patent Application No. 7-169974. While a detailed explanation is omitted herein, this approach makes it possible to define intended lightly doped regions 36, 37 which are approximately equal in width to the resultant anodized oxide as formed by anodization of the side wall of the gate electrode. Further, Unexamined Published Japanese Patent Application No. 7-169974 discloses therein a transistor structure, wherein the gate electrode 35 is far from the lightly doped regions 36, 37 by a specific distance equivalent to the thickness x.sub.3 of an anodized oxide 39 covering the gate electrode 35 in a strict sense, as shown in FIG. 3D.
While the offset gate structure is a simple and easy-to-fabricate structure, it unfortunately remains less effective at electric field reduction. In contrast, the LDD structure has a significant electric-field reduction effect, but suffers from the necessity of performing additional doping processes. A structure has been proposed as one approach to avoiding these problems, which permits formation of an intended region capable of exhibiting similar functions as those of the lightly-doped drain. This structure applies an electric field thereto as shown in FIG. 4 rather than by doping impurities thereinto. The offset structure of the field effect type as suggested by Examined Published Japanese Patent Application No. 8-17238.
As apparent from viewing FIG. 4, this field-effect offset gate transistor has a source 42, drain 43, active layer 41, gate insulation film 44 and gate electrode 45. The gate electrode 45 is spaced apart from drain 43, thereby providing the offset gate structure and wherein a second gate electrode 40 is provided overlying this part with a dielectric layer 49 being sandwiched therebetween. The dielectric layer 49 may be made of a chosen dielectric material obtainable by anodization of gate electrode 45.
In this structure, the drain is of N type conductivity. A positive bias voltage is applied to the second gate electrode 40 forming a weak inversion layer at a part 47 underlying the second gate electrode 40. Since this is similar in function to drains of lightly doped or "weak" N type conductivity, the region 47 exhibits similar effects to lightly-doped drains. If the source and drain are of P type conductivity, then the voltage applied to the second gate electrode is potentially reversed into the negative polarity.
While the structure discussed above requires no additional doping processes for formation of the lightly-doped impurity region, this does not come without accompanying a penalty: it does require additional formation of the second gate electrode 40, which in turn increases complexity of the fabrication process thereby making it impossible to offer advantages over the prior art LDD transistor structures.